Receive path implementation for an intermediate frequency transceiver
US6148048A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/28
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receive path implementation for an intermediate frequency (IF) transceiver is disclosed that provides increased signal processing integrity and accuracy with an efficient and improved design. A complex filter for a bandpass delta-sigma analog-to-digital converter (ADC) provides efficient complex noise shaping with a combination of real and complex filters. An automatic gain control (AGC) amplifier provides a constant bandwidth and zero variation phase shift for all gain levels. Clock adjust circuitry provides a clock signal with a jitter-free edge and a high percentage duty cycle. A fixed-gain input amplifier provides a matched input impedance. A method for choosing design specifications provides improved anti-aliasing properties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.