Apparatus and method for detection and recovery from structural stalls in a multi-level non-blocking cache system
US6148372A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Jan 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level cache and method for operation thereof is presented for processing multiple cache system accesses simultaneously. The cache includes a first non-blocking cache receiving data access requests from a device in a processor, and a first miss queue storing entries corresponding to data access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided and receives data access requests from the first miss queue, and a second miss queue stores entries corresponding to data access requests not serviced by the second non-blocking cache. A first arbiter arbitrates between two or more access requests to the first non-blocking cache. A second arbiter can be provided to arbitrate between two or more access requests to the second non-blocking cache. The arbiter is capable of determining if an anticipatory stall signal should be asserted if any of the cache resources, such as a queuing structure, is becoming overloaded. Under such conditions, the arbiter anticipatorily asserts the stall signal to cut-off new cache access requests from the front-end of the processor. The arbiter then dynamically reprioritizes the pending access requests to the cache…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.