Address generator circuity for a circular buffer
US6148386A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1998 |
| Grant date | Nov 14, 2000 |
| Priority date | — |
| Expiry date | Mar 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved apparatus and method for providing addresses for accessing circular memory buffers is provided. An apparatus comprised of a first feedback circuit, a second feedback circuit, a beginning address register, an ending address register, and a comparator circuit. A control circuit is also provided. The beginning and ending address registers preferably include the beginning and ending addresses respectively of a circular memory buffer. The first feedback circuit is comprised of a first register, a first phase delay register, a first adder, a first displacement register, and a first multiplexer. The second feedback circuit is preferably comprised of a second register, a second phase delay register, a second adder, and a second displacement register. Preferably the control circuit based at least partially on contents of the first register, beginning address register, and ending address register, and upon a comparison by the comparison circuit between the contents of the second register and the ending address register causes either the first register or the second register contents to be supplied to an address bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.