Method of forming a cob dram by using self-aligned node and bit line contact plug
US6150213A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1998 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Jul 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
Abstract
The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed over the dielectric film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.