Method and pattern for avoiding micro-loading effect in an etching process
US6150678A · kind A · utility
9Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1999 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Feb 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.