Lead frame for semiconductor package and lead frame plating method
US6150713A · kind A · utility
14Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1999 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Mar 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead frame plating method including the steps of (a) forming an intermediate layer on the upper surface of a metal substrate, (b) submerging the metal substrate into a plating solution, and (c) forming a passive layer to a thickness of 0.01 to 1.5 microinches on the upper surface of the intermediate layer by applying a modulated current to the plating solution and the metal substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.