Phase locked loops including analog multiplier networks that can provide constant loop bandwidth
US6150857A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1998 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Oct 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase locked loops include an analog multiplier network, wherein the loop filter and the analog multiplier network are serially connected between the phase detector and the controlled oscillator of the phase locked loop. The analog multiplier network does not require an external network or digital signals from a digital bus. The analog multiplier network can provide an analog linearizer that equalizes the loop bandwidth of the phase locked loop as a function of frequency. More specifically, the analog multiplier network equalizes the loop bandwidth of the phase locked loop as a function of frequency, to provide constant loop bandwidth for the phase locked loop as a function of frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.