Stable delay buffer
US6150862A · kind A · utility
36Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1998 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00143
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.