Serial to parallel converter enabled by multiplexed flip-flop counters
US6150965A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2000 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Mar 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parallel to serial converter comprising a parallel word latch for receiving a series of words comprised of parallel data words, a shift register for receiving the parallel data words and for storing bits of a parallel data word in a series of shift register stages upon receipt of a first enable signal, and for providing a serial stream of bits at a serial clock rate, a circuit for receiving a serial clock signal and for providing the serial clock signal to the shift register to enable shifting of the stored bits to an output as the serial stream of bits, and a controller for generating the enable signal and for applying the enable signal to the shift register and parallel word latch, said controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.