Dynamic semiconductor memory device
US6151244A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1998 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Oct 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.