Apparatus, system and method for control of speed of operation and power consumption of a memory
US6151262A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1999 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Oct 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention concerns power consumption control of memory having a fully powered state and at least one lower power state. The invention changes the memory to the fully powered state upon receipt of a memory access request. This memory access request is serviced in the fully powered state. The memory is returned to a lower power state after expiration of a grace period following a last memory access request. This grace period can be measured by a predetermined time or a predetermined number of memory access requests or a combination of these factors. The predetermined time may be fixed in manufacture or programmable in operation via a control register or data stored in a predetermined set of address locations within the address space of the memory. This invention is useful in portable electronic devices such as wireless telephones.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.