DMA controller of a RAID storage controller with integrated XOR parity computation capability adapted to compute parity in parallel with the transfer of data segments
US6151641A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DMA controller including an XOR FIFO buffer and XOR circuitry for computation of parity. The DMA controller resides within a RAID controller and establishes a direct data connection from host memory to subsystem local memory in order allow the CPU to perform other functions. The DMA controller accesses data segments from host memory corresponding to blocks of data within a disk stripe. As the data is transferred from host memory to subsystem local memory, the XOR circuitry simultaneously computes the parity corresponding to the successive data segments. Computing parity substantially simultaneously with the DMA data transfer reduces memory bandwidth utilization on the memory bus of the RAID controller. The parity is stored in the XOR buffer. Once parity is computed for a portion of data segments corresponding to a data stripe, the parity is transferred to local memory for retention. These steps are repeated until the full stripe is read into local memory and a parity value is computed for the entire data stripe. Once the RAID controller is ready to post the data to disk, the data is transferred from local memory to disk. The DMA controller of the present invention may also be adv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.