Detecting and isolating errors occurring in data communication in a multiple processor system
US6151689A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1996 |
| Grant date | Nov 21, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.