Ferroelectric capacitor, method of manufacturing same and memory cell using same
US6153898A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Jul 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/684
Abstract
A ferroelectric capacitor and a method of manufacturing the same are provided for reducing a crystal grain size while maintaining excellent ferroelectric properties so as to achieve a reduction in device size. A lower electrode, a ferroelectric layer and an upper electrode are formed on a substrate. The ferroelectric layer is formed into a plurality of stacked layers including an oxide of a layered crystal structure (Bi.sub.x (Sr, Ca, Ba).sub.y (Ta, Nb).sub.2 O.sub.9 .+-..sub.d). Proportion `y` of (Sr, Ca, Ba) in at least one of the layers is different from those of the other layers. That is, a variation in proportion `y` of (Sr, Ca, Ba) is provided in the ferroelectric layer. As a result, excellent ferroelectric properties are obtained and the crystal grain size of the oxide is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.