MOS transistor with high output voltage endurance
US6153916A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Apr 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An MOS transistor with high output voltage endurance comprises a semiconductor substrate with the surface thereof including a doping area having a surface doping concentration decreasing from the drain connection area to the drain-side edge of the gate oxide layer. This doping area is formed by ion implantation and subsequent outdiffusion of individual partial areas. The first partial area has a size in the drain-gate extension which is considerably larger than the penetration depth of the outdiffusion in the substrate. The second partial area has a size and a distance to the first partial area which are both smaller than the penetration depth of the outdiffusion in the substrate. In the outdiffused condition, the individual diffusions originating from the individual, respectively adjacent first and second partial areas merge into each other on the surface of the substrate to thus obtain a doping concentration gradient for a constant conduction type of the doping area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.