Voltage ratio regulator circuit for a spacer electrode of a flat panel display screen
US6153986A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2329/8645
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A voltage ratio regulator circuit for a spacer electrode of a flat panel display screen. Within one implementation of a field emission display (FED) device, thin spacer walls are inserted between a high voltage (Vh) faceplate and a backplate to secure these structures as a vacuum is formed between. A phosphor layer on the faceplate receives electrons selectively emitted from discrete electron emitting areas along the backplate (cathode) thereby forming images on the faceplate. The faceplate warms relative to the backplate, as a result of energy released by the phosphor layer, thereby generating a temperature gradient along the spacer walls. The top portion of each spacer wall becomes more conductive with increased temperature and acts to attract electrons that are emitted toward the faceplate. To counter this attraction, a spacer electrode is placed along each spacer wall at a height, d, above the backplate and maintained at a voltage, Ve. Electrodes of all of the spacer walls are coupled together. The spacer electrode at Ve and the high voltage supply at Vh are both coupled to a voltage ratio regulator circuit which maintains the ratio (Ve/Vh) using voltage dividers, an operationa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.