Apparatus and method for interfacing integrated circuits having incompatible I/O signal levels
US6154066A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/028
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for interfacing integrated circuits having incompatible input-output signal offset voltages that is relatively inexpensive and yet is also insensitive to noise. The apparatus of the present invention includes a receiver circuit for receiving differential signals on a differential line, comprising: (1) an interface circuit coupled to the differential signal line for removing a first offset voltage from the differential signal and biasing the differential signal to generate a biased differential signal having a second offset voltage, the interface circuit including a plurality of capacitive devices, (2) a differential amplifier circuit coupled to the interface circuit for converting the biased differential signal into a single-ended signal, (3) a Schmitt trigger circuit coupled to the differential amplifier circuit for filtering the single-ended signal to generate a filtered single-ended signal and (4) a latch circuit coupled to the Schmitt trigger circuit for filtering and asynchronously latching the filtered single-ended signal to generate a sustained, filtered digital signal. The method of the present invention comprises the steps of: (1) capacitively remov…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.