Circuits for preventing unwanted output transients in amplifiers during power-up
US6154092A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Nov 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0863
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention reduces certain unwanted transients in an output stage by sensing the power supply and disabling the output stage output devices in correlation with the sensing of an invalid bias. In preferred embodiments, the bias is measured at a node that is the last bias node to reach a steady state during power up or power glitches. This ensures that all portions of the output stage are being provided a valid bias prior to enabling the output devices of the output stage. By enabling the output devices only after a valid bias is present, signals generated by the output devices are based upon valid operation of the output stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.