Digital-to-analog converter D.C. offset correction comparing converter input and output signals
US6154158A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for adaptively correcting D.C. offset errors imposed upon signals in a communication device. The present invention includes a feedback loop correction circuit and method for measuring and reducing D.C. offset errors imposed upon analog transmission signals by transmit digital-to-analog converters (DACs) and associated analog reconstruction filters. A digital feedback loop is used to remove the D.C. offset errors from the analog transmission signals prior to transmission. In the preferred embodiment, the digital feedback loop includes a pair of analog-to-digital converters, a digital D.C. offset correction circuit, and a pair of adders. The transmission signals are digitized, filtered, and digitally processed by the correction circuit to generate offset correction signals that are equal to the undesired D.C. offset error present in the transmission signals. The correction signals are added to the digital input baseband signals thereby removing the undesirable D.C. offset errors from the transmission signals. In one preferred embodiment, the analog-to-digital converters comprise differential comparators that generate digital signals representative of the signs …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.