Successive approximation shift register with reduced latency
US6154163A · kind A · utility
4Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.