Method for designing a memory tile for use in a tiled memory
US6154413A · kind A · utility
32Cited by
2References
244Claims
0Family size
Inventors
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c', 32c").
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.