Method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory
US6154419A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2000 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Mar 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory is provided. While memory accessing agents, such a microprocessors, typically have a fixed memory access size (e.g., number of bits or bytes exchanged with a memory device in a single operation), DDR memory provides twice the memory burst capability of SDRAM. A method and apparatus is provided to allow memory access agents to exchange data with both SDRAM and DDR memory. Smaller groups of data may be combined or larger groups of data may be separated to allow compatibility. Buffering is provided to accommodate proper timing. Both SDRAM and DDR memory may be used simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.