Method for using wafer navigation to reduce testing times of integrated circuit wafers
US6154714A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1997 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Nov 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing an integrated circuit wafer is described, wherein the wafer has a first plurality of dice defined thereon, and at least one die has at least one known defect. The method comprises the steps of selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to the first die, determining, based upon the analysis, a probability of failure for each known defect on the first die, and modifying the sequence of tests performed on the first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.