Communication system for an array of direct access storage devices (DASD) that provides for bypassing one or multiple DASD
US6154791A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1997 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Jun 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit. Besides being serially connected to form a single communication path, the loop resiliency circuits can be divided into groups wherein the loop resiliency circuits in each group are serially connected to form a communication path. Se…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.