Microprocessor
US6154830A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
On a microprocessor chip mounting a central processing unit (CPU) for controlling the entire operation of electronic equipment and a digital signal processor (DSP) for processing a specific signal in the electronic equipment, an instruction cache for temporarily storing a DSP program and a cache controller are additionally mounted, and the DSP program and a CPU program are stored in an externally provided instruction memory. The cache controller controls the DSP to wait and interrupts the CPU when a cache miss occurs. The CPU executes a predetermined interrupt processing routine so as to supplement an instruction block including the instruction code from the instruction memory to the instruction cache. Thus, an on-chip memory used for storing instruction codes to be decoded and executed by the DSP can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.