Power failure safe computer architecture
US6154845A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1998 |
| Grant date | Nov 28, 2000 |
| Priority date | — |
| Expiry date | Sep 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.