Deep submicron MOS transistors with a self-aligned gate electrode
US6155537A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Jul 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions. The MOS transistor is characterized as having the following structure: (a) a substrate having a source region and a drain region; (b) a gate oxide layer on the substrate which overlays the source and drain regions, the gate oxide layer containing a central portion and two side portions, the central portion being a non-doped, and the side portions being lightly doped with a dopant; (c) a gate electrode formed on the gate oxide layer, the gate electrode having a base self-aligned with the central non-doped portion of the gate oxide layer; (d) a pair of sidewall spacers formed on sidewalls of the gate electrode, each of the sidewall spacers having a base self-aligned with a respective lightly doped side portion of the gate oxide layer; and (e) a pair of non-contiguous lightly dopes drain (LDD) sub-regions formed in the substrate. The LDD sub-regions respectively underlie the lightly doped side portions of the gate oxide layer and are formed by thermal diffusion of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.