Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays

US6157056A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Yuji Takeuchi · Kobe, JP
• Toshiharu Watanabe · Minokamo, JP
• Seiichi Aritome · Boise, US
• Hiroshi Watanabe · Funabashi, JP
• Kazuhiro Shimizu · Yokohama, JP

Key dates

• Filing date: Jan 16, 1998
• Grant date: Dec 5, 2000
• Expiry date: Jan 16, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

The semiconductor memory device comprises first and second memory cell rows each constructed by connecting a plurality of memory cell transistors, and third and fourth memory cell rows which are provided to be respectively adjacent to the first and second memory cell rows, such that element separation regions are respectively provided between adjacent memory cell rows. First and second transistors are connected between a drain or a source of the first memory cell row and a drain or a source of the second memory cell row. Gate electrodes of the first and third transistors are connected by a first gate line, and gate electrodes of the second and fourth transistors are connected by a second gate line. The first and second transistors are connected to a data line by a first contact. The third and fourth transistors are connected to a data line by a second contact. A first spacing element is connected between the first and second transistors and a second spacing element is connected between the third and fourth transistors, so that the distance between the first and second contacts is widened. The first contact is provided between the first transistor and the first spacing element. The …