Semiconductor device using a chip scale package
US6157080A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Nov 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package which eliminates the possibility of damages to a solder connected portion of a flip-chip connected chip by load, or which eliminates ultrasonic output at the time of wire bonding is described. Electrodes of a first chip are connected to first connection pads corresponding to the electrodes with the first chip being bonded at its rear surface to a rear surface of a second chip. A first resin is interposed in a gap between the first chip and a circuit board so as not to cover the first or second connection pads. Thereafter, the electrode of the second chip is connected to the second connection pads by wires, and the whole device is overlayed by a second resin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.