On-chip termination
US6157206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits include an impedance control circuit having at least one output terminal coupled to an on-chip reference termination device in order to control output impedance of the reference termination device such that it matches that of an external resistance. The impedance control circuit outputs are also coupled to the on-chip impedance-controlled termination devices which are coupled to each of the external transmission lines to be terminated. In this way, a single reference resistance allows many transmission lines to be properly terminated. The impedance-controlled termination devices are may be implemented as pairs of binary weighted p-channel and n-channel field effect transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.