Method and apparatus for clock uncertainty minimization with a clean power source
US6157250A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Jul 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09345
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.