Biasing and sizing of the MOS transistor in weak inversion for low voltage applications
US6157259A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Apr 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45674
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and circuits are disclosed for low voltage (1.5 Volt and below) CMOS circuits, offering good transconductance and current driving capabilities. These goals are achieved by biasing CMOS transistors in the weak inversion region, by utilizing multiple unit-sized transistors with a fixed gate width to gate length ratio, and by maintaining a uniform threshold voltage of each unit-sized transistor. The required transistor size is obtained by parallel connection of several unit-sized transistors, such that `n` unit sized transistors carry the required current of `n` units. The methods and circuits disclosed eliminate deviation of the output current of current mirrors caused by threshold voltage mismatch. Disclosed are a current mirror and two typical amplifiers as examples of weak inversion design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.