Phase-locked loop with tunable oscillator
US6157264A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phased-lock loop is disclosed for capturing the frequency of the input signal by adjusting a tunable oscillator such that a zero-crossing detector detects a zero-crossing point of the input signal relative to a predetermined number of counts at a counter where a control logic increments a tuning counter to increase the frequency at the tunable oscillator while decrements the tuning counter to decrease the frequency in the tunable oscillator. The predetermined number of counts at the counter representing one period, a fraction of a period, or a multiple of a period of the frequency of the input signal. The control logic adjusts the count at the tuning counter until the tunable oscillator generates an internal frequency that captures the frequency of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.