Rapid tuning, low distortion digital direct modulation phase locked loop and method therefor
US6157271A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Nov 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A direct modulation phase lock loop (PLL) a voltage controlled oscillator (VCO) (114). A divider (118) has a first divider input coupled to the VCO and a second divider input to receive a modulation inducing divisor sequence. A phase detector (102) has a first detector input coupled to the divider to receive the output thereof, and a second detector input to receive a reference input. A tuning circuit (306, 406) is coupled to the phase detector and the VCO, the tuning circuit responsive to a variable DC reference potential such that the tuning circuit has a frequency response that is constant over the modulation bandwidth whereby the PLL is a type 1 PLL with low modulation distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.