Synchronization of frame buffer swapping in multi-pipeline computer graphics display systems
US6157395A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 19, 1997 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | May 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronization of frame buffer swapping among computer graphics pipelines in a multi-pipeline display system: The pipelines are arranged in a closed daisy chain loop. One pipeline is configured as master; the others are configured as slaves. The master swaps its frame buffers and propagates a master swap signal through the daisy chain. As each slave recognizes the signal, it swaps its own buffers. Each slave propagates a feedback signal back to the master to indicate whether the slave is ready to swap its buffers again. The master waits until the feedback signal indicates that all slaves are ready to swap their buffers before the master will swap its own buffers a second time. The process repeats when the master swaps its buffers a second time. A first synchronization control system is coupled to a first pipeline and has a first daisy chain input and a first daisy chain output. A second synchronization control system is coupled to a second pipeline and has a second daisy chain input and a second daisy chain output. The first synchronization control system asserts the first daisy chain output when the first pipeline swaps its buffers and unasserts the first daisy chain output when …
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