Apparatus and method for processing packetized information over a serial bus
US6157972A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Nov 20, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S370/912
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.