Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system
US6157989A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Jun 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arbitration and task switching technique in a real-time multiprocessor data processing system (20) having a common bus (32) and a segmented shared memory (30), where fullness of memory segments of the shared memory (30) is used as a measurement for arbitration and task switching priorities. A bus request mechanism in each of the processors dynamically calculates normalized priority values based on relative needs across the system (20). The normalized priority calculation is based on monitoring the fullness of memory segments of the shared memory (30) associated with each processor (24, 26, 28) of the system (20). Using this normalized priority calculation, the bus access order and bus bandwidth are optimally allocated according to tasks executed by the processors (24, 26, 28). Also, the normalized priority calculation and a preprogrammed threshold is used to control task switching in the multi-processor system (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.