Independent chip select for SRAM and DRAM in a multi-port RAM
US6157990A · kind A · utility
8Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1998 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Jan 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port RAM (MPRAM) having a SRAM and a DRAM on a single chip. Separate pins are provided on the chip to supply independent chip select signals for the SRAM and the DRAM. When the SRAM chip select signal is at a high level, a clock generator is prevented from producing an internal clock signal for the SRAM. As a result, no SRAM operation is performed in response to a SRAM command. Similarly, when the DRAM chip select signal is high, a clock generator produces no internal clock signal for the DRAM. As a result, DRAM operations are prevented from being performed in response to DRAM commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.