Integrated circuit including patching circuitry to bypass portions of an internally flawed read only memory and a method therefore
US6158018A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Dec 5, 2000 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/328
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved Integrated Circuit (IC) device is delineated comprising, in combination, an IC including an embedded Digital Signal Processor (DSP), an embedded Random Access Memory (RAM), an embedded Read Only Memory (ROM) having at least one portion thereof which is flawed and embedded patching circuitry having as inputs the current DSP program address and at least one break address wherein each break address corresponds to a separate flawed portion of the embedded ROM. The patching circuitry supplies data stored in flawless portions of the ROM to the DSP until the current DSP program address matches a break address indicating that the next portion of the embedded ROM is flawed. In place of the data stored in the flawed portion of the embedded ROM, the patching circuitry supplies corrected data stored in the embedded RAM to the DSP, and after this corrected data is supplied, data transfer to the DSP from the remaining unflawed portions of the embedded ROM is resumed. If flawed portions in the embedded ROM are subsequently detected, the aforementioned process repeats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.