Electrical resistance with at least two contact fields on a ceramic substrate and process for manufacturing the same
US6159386A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Jun 10, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/0394
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A temperature-dependent measuring resistance with rapid response time is at least partially arranged on an electrically insulating surface of a ceramic substrate, wherein a portion of the conductor path spans a recess situated in the substrate in a bridge-like manner, and the remaining portion of the conductor path in the edge area of the substrate adjacent to the recess is provided with connection contact fields. The conductor path comprises a platinum or gold layer, wherein the conductor path is partially provided with a cover layer of glass, and wherein the connection contact fields are exposed. In a further embodiment, the conductor path is arranged together with the connection contact fields either on a screen-printed glass membrane or on a thin film membrane applied in a PVD process, which covers the surface of the ceramic substrate and spans the recess. The cover layer is likewise selectively applied by screen printing in case there is a glass membrane. In the case of a thin film membrane, the cover layer is also applied selectively by a PVD process and can be the same material as the thin film membrane. The ceramic substrate preferably comprises aluminum oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.