Semiconductor wafer and fabrication method of a semiconductor chip
US6159826A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Sep 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present invention, a semiconductor wafer containing a plurality of semiconductor chip portions has a plurality of chip scribe lanes formed between the semiconductor chip portions. A plurality of chip bonding pads are formed on the semiconductor chip portions of the wafer, and a plurality of wafer probing pads are formed on the chip scribe lanes. The wafer probing pads are electrically connected to internal circuits of the semiconductor chip portions and/or to corresponding ones of the chip bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.