Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the bit lines
US6160297A · kind A · utility
69Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Feb 3, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arranged at intervals of plural bit lines BL. The source line is led to a source line contact through a conductive member composed of a low-resistance metal in the same manner as a bit line contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.