Patent · US Expired

Programmable interconnect architecture

US6160420A · kind A · utility

38Cited by
324References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 12, 1996
Grant dateDec 12, 2000
Priority date—
Expiry dateNov 12, 2016

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K19/17736
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.