Ninety-degree phase shifter
US6160434A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Oct 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained. With this configuration provided is a 90-degree phase shifter which achieves the uniform input load to improve a phase offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.