Video signal processing circuit inhibiting display of distorted images
US6160590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Mar 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/45
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video signal processing circuit uses a buffer memory for reducing or expanding video signals in the generation of child images to be displayed within a display window. Image size data, stored in a header within the buffer memory, and a reduced video signal are prevented from representing different image reduction ratios which might otherwise occur when the reduction ratio is changed. At the time of changing the reduction ratio, image size data SIZ are calculated from a write enable signal based on reduction ratio data K, for a one-field period just after the change by an input video clock generator 22. The calculated image size data are written to a header together with a reduced video signal in a field memory 2, and a flag bit SP indicating the change in the reduction ratio is also written to the header for the one-field period just after the change. When data are read from the buffer memory, the flag bit SP is detected by a display video clock generator 23 to mute a video signal output when there is a likelihood of displaying distorted data. On the other hand, writing to the field memory 2 is inhibited for the one-field period just after the change in the image magnification da…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.