Associative memory and method for the operation thereof
US6160729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1998 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Sep 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An associative memory contains cells that are formed of a series circuit of an ordinary PMOS transistor with a PMOS transistor with a floating gate. The ordinary PMOS transistor receives of an input vector and the gate of the second PMOS transistor is connected to a learning input. For the associative access, a second vector can be applied to the drain terminal of the second PMOS transistor and, upon readout, the current flow through the respective series circuit is evaluated column-by-column by current evaluator circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.