Configuration for crosstalk attenuation in word lines of DRAM circuits
US6160747A · kind A · utility
4Cited by
5References
5Claims
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Key dates
| Filing date | May 28, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, includes a decoder provided at a first end of a word line, and a holding transistor. A pull-down device is provided as a "noise killer" at a second end of the word line, which opposite the first end. The pull-down device pulls down the potential of the word line in a standby and hold mode in the event of an active adjacent word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.