Storage subsystem including an error correcting cache and means for performing memory to memory transfers
US6161208A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1999 |
| Grant date | Dec 12, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage subsystem for use in a data processing system having real and extended storage, a vector processor and a store-in cache buffer. Transfers between real and extended storage are performed with a store buffer external to the cache, but comparable in size to the line size of the cache directly associated with the real storage. Hard data errors in the cache are corrected with hardware invert-retry mechanism which operates in response to a machine check and does the correction as a part of the instruction retry. Vector processor storage operations bypass the cache and transfer data directly from storage to the vector processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.