Clock loss detector
US6163172A · kind A · utility
16Cited by
10References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Nov 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when docks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.