Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance
US6163173A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | May 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for implementing adjustable logic threshold in dynamic circuits. The dynamic circuit includes an intermediate precharge node. An output logic stage is connected to the intermediate precharge node. A threshold adjustment circuit is connected to the output logic stage. The threshold adjustment circuit receives a selection input to adjust a threshold of the output logic stage. The threshold adjustment circuit is formed of a first transistor and a second transistor coupled in parallel with a pair of series connected transistors included in the output logic stage. One or both of the first transistor and second transistor are selectively activated to adjust the threshold of the output logic stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.